1. Field of the Invention
The present invention relates generally to a method for making a stacked electrode for a semiconductor device and specifically to a stacked gate electrode structure for a semiconductor device.
2. Description of the Related Art
Semiconductor devices such as flash EEPROM (electrically erasable programmable read only memory) devices are provided with stacked gate electrode structures. Other semiconductor devices include stacked electrode structures as well. A typical stacked gate electrode structure includes three layers which are, for example, a first conductive layer, an insulating layer, and a second conductive layer that together are formed on a gate oxide layer at the surface of the semiconductor substrate. These layers are patterned, or shaped, to provide the stacked structure of the electrode. The formation of the stacked gate electrode structure is shown as an idealized example illustrated in FIGS. 4A through 4C.
In FIG. 4A, first, a gate oxide layer 11 is formed by well known layer forming methods on a surface of a semiconductor substrate 10 which is a silicon semiconductor substrate. Next, a first conductive layer 12 is formed on the gate oxide layer 11, followed by an insulating layer 13, and then a second conductive layer 14. The first conductive layer 12 is of a polycrystalline silicon layer that is formed by a CVD (chemical vapor deposition) method and is doped with impurities. The insulating layer 13 is formed of a material referred to as ONO by CVD methods or by oxidation methods. The ONO material is SiO.sub.2 /SiN/SiO.sub.2. The second semiconductor layer 14 has a polycide structure it is formed of a polycrystalline silicon layer 14A that is formed by a CVD method and doped with impurities and a metallic-silicide layer 14B which is formed by a sputtering method. The metallic-silicide layer in one example is tungsten-silicide.
A photoresist 15 is formed on the second conductive layer 14 and then the photoresist 15 is patterned, resulting in the structure illustrated in cross section in FIG. 4A.
The FIG. 4B shows the next steps in the manufacturing process. The second conductive layer 14 is patterned using HBr as an etching gas by a RIE (reactive ion etching) method. The insulating layer 13 is patterned using CHF.sub.3 /CF.sub.4 as the etching gas. The photoresist 15 which was previously patterned serves as the etching mask for these etching steps. The resulting structure is shown in the cross section of FIG. 4B.
The first conductive layer 12 is then etched, or patterned by the RIE (reactive ion etching) method using, for example, Cl.sub.2 /HBr as an etching gas. The photoresist 15 also serves as the etching mask during this patterning step. Subsequently, the photoresist 15 is removed. The resulting structure is a stacked gate electrode structure such as shown in FIG. 4C in cross section. When this stacked gate electrode structure is used in a flash EEPROM semiconductor device, the patterned second conductive layer 14 serves as a control gate and the patterned first conductive layer 12 serves as a floating gate.
When the stacked gate electrode structure as shown in FIGS. 4A through 4C is intended to be formed, a side wall covering layer 20 accumulates on the sides of both the second conductive layer 14 and the insulating layer 13 when the insulating layer 13 is being patterned in the actual carrying out of the process described above. This side wall covering layer 20 is shown in FIG. 5A, and is principally formed of CH.sub.x F.sub.y as the main ingredient. This side wall covering layer 20 is primarily formed by a reaction of the photoresist 15 or by a reaction of the carbon discharged from the material of an electrode of the dry etching apparatus reacting with the etching gas. If the patterning of the first conductive layer 12 is carried out while the side wall covering layer 20 is present then the side wall covering layer 20 functions as an etching mask as shown in FIG. 5B so that the result is the first conductive layer 12 is of a greater width than expected. Thus, the gate length is longer than the layers above it.
If the insulating layer 13 and the first conductive layer 12 are of different widths, a difference in capacitance is generated between the gate oxide layer 11 and the insulating layer 13 so that problems are caused such as that data writing to the flash EEPROM is delayed and data reading is changed. Furthermore, a problem also arises when forming the so-called gate side wall on the sides of the gate electrode. In addition, the above gate length variation causes transistor characteristics to vary.